Conventionally, when manufacturing a semiconductor device or the like, there has been widely used an ion implanting technique as a method for introducing impurities into a semiconductor substrate, a semiconductor layer, or the like. In a conventional ion implanting technique, in order to implant desired atoms/molecules with a predetermined concentration into a target object such as a semiconductor substrate or a semiconductor layer, a positively charged ion beam is irradiated onto a desired spot of the target object. Accordingly, positively charged ions are irradiated onto the target object and secondary electrons are emitted from the target object, so that the target object is largely charged up and thus charge-up damage may occur thereon. For example, if ions are irradiated onto a polysilicon gate electrode layer on a gate insulating film in order to dope impurities into the polysilicon gate electrode layer, a large quantity of secondary electrons are emitted from the polysilicon layer and positive charges are accumulated on a surface of the polysilicon layer, and positive charges of the implanted ions are added thereon, whereby a large quantity of negative charges are accumulated on the gate insulating film. Meanwhile, if ions are implanted into a n-well in order to form a p-type source/drain region, a large quantity of positive charges are accumulated on a surface of the n-well for the same reason, thereby causing a breakdown of the gate insulating film. Therefore, product failure has often occurred in a p-channel MOS transistor.
Meanwhile, disclosed in Patent Document 1 is an ion implanting apparatus including a processing chamber having a plurality of exhaust ports; a holding table installed within the processing chamber, for holding a target object; a shower plate disposed to face the target object and having a plurality of gas discharge holes; and a microwave antenna.
Patent Document 1: Japanese Patent Laid-open Publication No. 2005-196994